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Revision Standard – Inactive-Withdrawn.The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.
Product Details
- Published:
- 09/28/2001
- ISBN(s):
- 0738126910, 9781504457279
- Number of Pages:
- 429
- File Size:
- 1 file , 1.8 MB
- Product Code(s):
- STDRE94959