The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
Product Details
- Edition:
- 3.0
- Published:
- 07/01/2021
- ISBN(s):
- 9782832299777
- Number of Pages:
- 1320
- File Size:
- 1 file , 16 MB
- Note:
- This product is unavailable in Belarus, Russia, Ukraine